a) Field of the Invention
The present invention relates generally to a semiconductor device, and more specifically to a semiconductor device having a MISFET the current-voltage characteristics of which can be evaluated during wafer processes.
b) Description of the Related Art
In order to evaluate the characteristics of a MISFET formed on a semiconductor substrate during manufacture processes of semiconductor devices, a process control monitor (PCM) transistor is formed in addition to desired electronic circuits. Generally, the gate electrode of MISFET in an electronic circuit is connected via an interconnect to an impurity diffusion region in a surface layer of a semiconductor substrate. The gate electrode of a PCM transistor is, however, unnecessary to be connected to the semiconductor substrate. If a plasma process or the like is performed under the condition that the gate electrode is not connected to the semiconductor substrate, electric charges are accumulated in the gate electrode, and the gate insulating film under the gate electrode becomes likely to have a dielectric breakdown. In order to prevent a dielectric breakdown of the gate insulating film, a gate protective element has been used.
FIG. 5 is a cross sectional view of a conventional PCM transistor and a gate protective element. A p-type silicon substrate 100 has a p-type well 101 formed in the surface layer of the substrate. A field oxide film 102 defines an active region in the surface layer of the p-type well 101.
One active region in the p-type well 101 has a MISFET formed therein. MISFET is constituted of a source region 103, a drain region 104, a gate electrode 105, and a gate insulating film 106. Another active region in the surface layer of the p-type well 101 has an n-type impurity diffusion region 107. The gate electrode 105 is connected via an interconnect 115 to the impurity diffusion region 107.
The source region 103, drain region 104, and gate electrode 105 are respectively connected to pads 109, 111, and 110 to which probes are connected. The p-type well 101 is connected to a pad 108. A desired voltage is applied to each pad 108 to 111 to measure the current-voltage characteristics of MISFET.
Electric charges accumulated in the gate electrode 105 during wafer processes flow into the substrate via the interconnect 115 and impurity diffusion region 107. If a breakdown voltage of a p-n junction between the impurity diffusion region 107 and p-type well 101 is set lower than a dielectric breakdown voltage of the gate insulating film 106, it is possible to prevent the dielectric breakdown of the gate insulating film 106.
Consider now that MISFET shown in FIG. 5 is an n-channel depletion type MISFET. Since the threshold voltage of this MISFET is negative, it is necessary to apply a negative voltage to the gate electrode 105 relative to the p-type well 101 in order to measure the threshold voltage. In this case, the p-n junction between the impurity diffusion region 107 and p-type well 101 is forward biased. If a voltage lower than -0.6 V is applied to the gate electrode 105, a forward current flows from the p-type well 101 to the impurity diffusion region 107.
This forward current makes an npn bipolar transistor ON state, the npn transistor having the impurity diffusion region 107, p-type well 101, and drain region 104 as its emitter, base, and collector. Therefore, the drain current of MISFET increases and the intrinsic characteristics of MISFET cannot be measured.